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<div class="textblock"><p>This file contains the implementation of the MIPI CSI2 RX Controller driver.User documentation for the driver functions is contained in this file in the form of comment blocks at the front of each function.</p>
<p><b>Core Features</b></p>
<p>The CSI2 Rx Controller currently supports the MIPI?Alliance Specification for Camera Serial Interface 2 (CSI-2) Version 1.1 ? 18 July 2012 with D-PHY v1.2.</p>
<p>There is a provision for multi-lane support for upto 4 lanes for receiving data upto 1.5 Gbps per lane. It supports both short and long packets. Most of the primary and secondary formats of images are supported along with interleaving of data at packet or frame level for upto 4 virtual channels in the stream. The IP has capability to detect Start of Transmission, CRC, ECC, etc type of errors and report them via interrupts.</p>
<p>The IP is programmable when the core is disabled or when the soft reset bit has been set and the reset-in-progress is reset.</p>
<p>The programmable parameters are the number of active lane counts, global interrupt enable and interrupt masks for variety of events to be detected.</p>
<p><b>Software Initialization &amp; Configuration</b></p>
<p>The application needs to do following steps in order for preparing the MIPI CSI2 Rx core to be ready to receive stream</p>
<ul>
<li>Call XCsi_LookupConfig using a device ID to find the core configuration.</li>
<li>Call XCsi_CfgInitialize to initialize the device and the driver instance associated with it.</li>
<li>Call XCsi_Configure to set the Active Lanes</li>
<li>Register callback functions for interrupts</li>
<li>Enable interrupts</li>
<li>Call XCsi_Activate to activate the core</li>
</ul>
<p><b> Interrupts </b></p>
<p>There are certain events for which interrupts are received if unmasked like</p>
<ul>
<li>Frame received</li>
<li>Incorrect Lane Configuration</li>
<li>Short Packet FIFO Full or Not Empty</li>
<li>Stream Line Buffer Full</li>
<li>Stop State</li>
<li>Start of Transmission (Sync) Errors</li>
<li>CRC and ECC errors</li>
<li>Invalid Data ID</li>
<li>Frame Sync and Level Errors for Virtual Channels</li>
</ul>
<p><b> Virtual Memory </b></p>
<p>This driver supports Virtual Memory. The RTOS is responsible for calculating the correct device base address in Virtual Memory space.</p>
<p><b> Threads </b></p>
<p>This driver is not thread safe. Any needs for threads or thread mutual exclusion must be satisfied by the layer above this driver.</p>
<p><b> Asserts </b></p>
<p>Asserts are used within all Xilinx drivers to enforce constraints on argument values. Asserts can be turned off on a system-wide basis by defining, at compile time, the NDEBUG identifier. By default, asserts are turned on and it is recommended that application developers leave asserts on during development.</p>
<pre>
MODIFICATION HISTORY:</pre><pre>Ver Who Date     Changes
</p>
<hr/>
<p>
1.0 vsa 06/16/15 Initial release
1.1 sss 08/17/16 Added 64 bit support
    ms  01/23/17 Modified xil_printf statement in main function for all
                 examples to ensure that "Successfully ran" and "Failed"
                 strings are available in all examples. This is a fix
                 for CR-965028.
    ms  03/17/17 Added readme.txt file in examples folder for doxygen
                 generation.
    ms  04/05/17 Modified Comment lines in functions of csi
                 examples to recognize it as documentation block
                 for doxygen generation of examples.
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